The present invention relates to semiconductor device manufacturing, and in particular to methods for forming semiconductor devices such as metal oxide semiconductor field effect transistors (MOSFETs) and anti-fuses which include at least a dual thickness dielectric layer.
In current technologies, the threshold voltage of semiconductor devices does not scale with the power supply voltage and ground rules because of the non-scalability of the sub-threshold slope. Thus, the minimum gate oxide thickness and/or maximum wordline boost voltage of the array MOSFET is constrained by reliability considerations.
When used for the support MOSFET, the relatively thick gate oxide (having a thickness of greater than ≈6 nm for deep sub-xcexcm technology) required by the array MOSFET results in degradation in the performance of the MOSFET device. Furthermore, if a thinner gate oxide is used to improve the performance of the support circuitry, charge transfer efficiency in the device array is compromised as a result of the reliability limitation of the wordline boost voltage.
Ideally, in such technology, a dual gate oxide thickness is desired. In the prior art, it is known to subject the array transistor to a dual gate oxidation process or an alternative gate oxidation process as compared to the support circuitry. These additional gate oxidation processing steps are costly, and they are also yield limiting since one must utilize additional processing steps such as, but not limited to: masking, exposure, etching, oxidizing and strip masking, which grow a second oxide on the entire structure of the MOSFET device. As such, prior art gate oxidation processes are not reliable nor cost efficient.
In view of the drawbacks mentioned above with prior art processes of fabricating MOSFETs, there is a continued need for providing a new and improved method of fabricating a MOSFET and other devices in which a dielectric layer, e.g., gate oxide, having a dual thickness can be formed without adding extra processing steps and costs to the overall manufacturing process.
One object of the present invention is to provide a self-aligned MOSFET having low overlap capacitance, and a low gate induced drain leakage (i.e., low electric field), with thin oxide MOSFET properties.
Another object of the present invention is to provide a method of forming a structure having lightly doped source/drain diffusion regions that are self-aligned with the step in the gate dielectric thickness. The term xe2x80x9cstepxe2x80x9d is used herein to denote the region in the gate dielectric wherein an abrupt change in dielectric thickness occurs.
A further object of the present invention is to provide an anti-fuse device in which significantly lower dielectric rupture voltages can be employed than heretofore possible with prior art anti-fuse devices.
An even further object of the present invention is to provide an anti-fuse device in which the programming region of the device is tailored made.
The above objects and advantages are achieved in one embodiment of the present invention by implanting an inhibiting species into predetermined regions of a semiconductor structure, whereby said inhibiting species retards the growth of a gate dielectric so as to form discrete dielectric regions having different thicknesses.
Specifically, in this embodiment of the present invention, the method comprises the steps of:
(a) forming a mask having an opening therethrough on a structure, said opening having sidewalls;
(b) implanting an inhibiting species into said structure through the opening so as to form an inhibiting region in said structure; and
(c) growing a dual thickness dielectric layer on the structure in said opening, wherein the inhibiting region partially inhibits growth of the dielectric layer.
The above-mentioned basic processing steps can be used in conjunction with or without sacrificial sidewall spacers formed in the opening, and with or without a sacrificial oxide layer formed in the opening. The above-mentioned processing steps may also be used in conjunction with a conventional damascene processing scheme or, alternatively, in conjunction with a non-damascene processing scheme.
Damascene processing is employed in the present invention in fabricating MOSFETs that have minium device geometry. Non-damascene processing, while being capable of forming MOSFETs, is limited to larger devices than which can be fabricated by damascene processing. Moreover, the non-damascene technique permits the formation-of anti-fuse devices that contain the dual thickness dielectric layer as the anti-fuse material.
Alternatively, the dual thickness dielectric may be obtained utilizing the following processing steps:
(axe2x80x2) forming a mask having an opening therethrough on a structure, said opening having sidewalls;
(bxe2x80x2) implanting a dielectric growth enhancement species into said structure through the opening so as to form an enhancing region in said structure; and
(cxe2x80x2) growing a dual thickness dielectric layer on the structure in said opening, wherein the enhancing region partially aids in growth of the dielectric layer.
This alternative embodiment of the present invention may be used with or without sacrificial sidewall spacers; without or without a sacrificial oxide layer; in conjunction with a damascene processing scheme; or in conjunction with a non-damascene processing scheme.
Notwithstanding which method is employed, the present invention also comprises a semiconductor device which includes a dual thickness dielectric as either the gate oxide of a MOSFET or as an anti-fuse material. Specifically, the semiconductor device of the present invention comprises:
a semiconductor substrate having a gate region formed thereon, wherein said semiconductor substrate and said gate region are separated by a dielectric that has a dual thickness associated therewith.
In one embodiment of the present invention, the structure contains lightly doped source/drain diffusion regions that are self-aligned with the step segment in the dual thickness dialectic.